This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-345586, filed Nov. 13, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor memory device and a method of operating the same. More particularly, the present invention relates to a NAND type EEPROM (electrically erasable programmable read only memory) in which each memory cell unit (NAND cell) is formed by serially connecting a plurality of memory cells in the column direction.
2. Description of the Related Art
EEPROMs are known as a type of semiconductor memory devices where data can be electrically rewritten. Of EEPROMs, NAND type EEPROMs have been attracting attention because they can be adapted to a high degree of integration.
Each of the memory cells of a NAND type EEPROM comprises a MOS transistor having a stack gate structure. The memory cells of each column are connected in series and any two adjacent memory cells, or MOS transistors, share a common source/drain to produce NAND cells. Then, such NAND cells are arranged in rows to form a NAND cell block. A plurality of NAND cell blocks are arranged in the column direction to produce a memory cell array.
The drains of the NAND cells of each column of a memory cell array are commonly connected to a bit line by way of a first selection gate transistor. Similarly, the sources of the NAND cells of each column are connected to a common source line (grounded) by way of a second selection gate transistor. On the other hand, the control gates of each memory cell of a plurality of NAND cells are commonly connected in the row direction to form word lines (control gate lines). Similarly, the gate electrodes of the first and second selection gate transistors are commonly connected to form selection gate lines.
The papers (1) and (2) listed below describe NAND type EEPROMs having such a configuration.
(1) K. -D. Suh et al., xe2x80x9cA 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Schemexe2x80x9d, IEEE J. Solid-State Circuits, Vol. 30, pp. 1149-1156, November 1995.
(2) Y. Iwata et al., xe2x80x9cA 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROMxe2x80x9d, IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995.
Now, the configuration of a known NAND type EEPROM will be described in greater detail by referring to the accompanying drawing.
FIG. 12 of the accompanying drawing is a schematic circuit diagram of memory cell array of a known NAND type EEPROM, showing only a NAND cell block NCB thereof.
Referring to FIG. 12, a NAND cell block NCB comprises a plurality of NAND cell units NCY arranged in rows. Each NAND cell unit NCY has NAND cells NC. Each NAND cells NC is formed by a plurality of memory cells M. Each memory cell M comprises a MOS transistor having a stack gate structure. In other words, a number of MOS transistors are connected in series in such a way that any two adjacent MOS transistors share a common source/drain. NAND cells NC are formed in this way.
The drain of the MOS transistor located at an end of the NAND cells NC arranged in each row is connected to a selection gate transistor S1. Each of the selection gate transistors S1 is connected to a bit line BLi (i=0, 1, 2, . . . ). The source of the MOS transistor located at the other end of the NAND cells NC arranged in each row is connected to another selection gate transistor S2. Each of the selection gate transistors S2 is connected to a common source line SL.
The control gates of memory cell M of the NAND cells NC arranged in each row are commonly connected to a word line WLj (j=0, 1, 2, . . . ). The gate electrodes of the selection gate transistors S1 are commonly connected to a selection gate line SSL. The gate electrodes of the selection gate transistors S2 are commonly connected to another selection gate line GSL.
Normally, a plurality of NAND cell blocks NCB, each having a configuration as described above, are arranged in the column direction to produce a memory cell array. Note that each bit line BLi and each common source line SL are shared by a plurality of NAND cell block arranged in the column direction.
Each NAND cell block NCB operates as a smallest unit for erasing data. In other words, data are collectively erased on a NAND cell block by NAND cell block basis. The memory cells M connected to a selected word line WLj in a NAND cell block NCB are referred to as a page. In other words, a page provides a unit for reading and writing data.
If each memory cell M is an n-channel MOS transistor, an operation of erasing data, that of reading data and that of writing data proceed in a manner as described below.
The E type state and the D type state of an n-channel MOS transistor are made to correspond to respective binary numbers. The E state refers to a state where the threshold value of the transistor is positive when electrons are injected into the floating gate. The D type state refers to a state where the threshold value of the transistor is negative when electrons are ejected from the floating gate. For instance, the D type state may be defined as a xe2x80x9c1xe2x80x9d data holding state (erased state), whereas the E type state may be defined as a xe2x80x9c0xe2x80x9d data holding state (written state). Then, an operation of shifting the threshold value of the memory cell M holding a xe2x80x9c1xe2x80x9d data to the positive direction into a state where the memory cell M is holding a xe2x80x9c0xe2x80x9d data is defined as xe2x80x9ca write operationxe2x80x9d. On the other hand, an operation of shifting the threshold value of the memory cell M holding a xe2x80x9c0xe2x80x9d data to the negative direction into a state where the memory cell M is holding a xe2x80x9c1xe2x80x9d data is defined as xe2x80x9can erase operationxe2x80x9d. The following description of the specification is based on the above definitions.
FIG. 13 of the accompanying drawing is a chart illustrating the bias voltage applied to a number of different parts of the selected NAND cell block (to be referred to simply as selected block hereinafter) NCB for an erase operation, a read operation and a write operation. Note that the memory cell M is an n-channel MOS transistor.
For a data erasing operation, OV is applied to all the word lines WLj of the selected block NCB. The selection gate lines SSL, GSL and the bit lines BLi are held to a floating (F) state. A high positive erase voltage Vera (e.g., a 21 V pulse voltage with a cycle period of 3 ms) is applied to the P-type well region (substrate) of the cell region. As a result, the erase voltage Vera is applied between the P-type well region and the word lines WLj. Then, the electrons in the floating gate are ejected into the P-type well region by the FN tunnel current. Thus, each of the memory cells M in the selected block NCB is brought to the erased state of holding a xe2x80x9c1xe2x80x9d data.
On the other hand, the potential of the word lines WLj of each unselected NAND cell blocks (to be referred to as unselected block hereinafter) NCB is raised by way of capacitive coupling of the word lines WLj in the floating state and the P-type well region. The capacitive coupling ratio will be computed from the capacitance connected to the word lines WLj that are in the floating state. As a matter of fact, the capacitance of the word lines that are made of polysilicon and that of the P-type well region is high relative to the total capacitance. Therefore, the FN tunnel current will be prevented from flowing. Additionally, the threshold voltage of each and every memory cell M in the selected block NCB is checked to see if it has fallen below xe2x88x921 V, for example for the purpose of verifying the erase operation.
For a data read operation, 0 V is applied to the selected word line WLj. A certain intermediary voltage Vread is applied to all the unselected word lines WLj and the selection gate lines SSL, GSL. The intermediary voltage Vread is a voltage necessary for making the channel region electrically conductive without relying on the threshold value. The data read operation is carried out by reading the change in the potential of the bit line BLi that takes place as a result of making the selected memory cell M electrically conductive or non-conductive.
Finally, for a data write operation, a high positive write voltage Vpgm is applied to the selected word line WLj. An intermediary voltage Vpass is applied to all the unselected word lines WLj. An operation voltage Vcc is applied to the selection gate line SSL located at the side of the bit lines BLi. The ground voltage Vss (=0 V) is applied to the selection gate line GSL located at the side of the common source lines SL. The ground voltage Vss is applied to the bit line BLi to be used for writing a xe2x80x9c0xe2x80x9d data and the operation voltage Vcc is applied to the bit lines BLi that need to be held to the erased state with a xe2x80x9c1xe2x80x9d data written thereto and where any write operation needs to be prohibited. At this time, the channel potential of the selected memory cell M connected to the bit line BLi to which the ground voltage Vss is applied is held to the ground potential Vss. As a result, a large electric field is applied between the control gate and the channel region. Then, electrons are injected from the channel region into the floating gate by the FN tunnel current. Note, however, that no sufficient electric field is applied to all the other unselected memory cells M that are connected to the same bit line BLi and to which the intermediary voltage Vpass is applied. Therefore, no electrons are injected into the floating gates of the unselected memory cells M by the FN tunnel current and hence no data is written to those memory cells M.
On the other hand, the memory cells M connected the bit line BLi to which the operation voltage Vcc is applied are cut off. In other words, the channel region of the NAND cell NC is preliminarily charged either to the operation voltage Vcc or to the voltage Vcc-Vth. As a result, the above memory cells M are cut off. Note that Vth is the threshold voltage of the selected memory cell M. Then, the write voltage Vpgm or the intermediary voltage Vpass is applied to the control gate of each and every cut off memory cell M. Thus, any injection of electrons is prevented from taking place. This is because the channel potential shows a rise due to the capacitive coupling of the channel region of the NAND cell NC that is in the floating state and the control gate to which the write voltage Vpgm or the intermediary voltage Vpass is applied.
In this way, electrons are injected only into the floating gate of the memory cell M located at the intersection of the bit line BLi to which the ground voltage Vss is applied and the selected word line WLj to which the write voltage Vpgm is applied. Thus, a xe2x80x9c0xe2x80x9d data is written to the memory cell M. On the other hand, the channel potential of each and every memory cell M in the selected block NCB to which any data is prohibited from being written is determined by the capacitive coupling of the word line WLj and the channel region of the NAND cell NC. Therefore, it is important to preliminarily charge the channel region with electricity to a satisfactory extent in order to sufficiently raise the write prohibition voltage.
Additionally, it is important to raise the capacitive coupling ratio between the word line WLj and the channel region.
The capacitive coupling ratio B between the word line WLj and the channel region is obtained by the formula shown below;
B=Cox/(Cox+Cj), 
where Cox is the total sum of the gate capacitances between the word lines WLj and the channel regions and Cj is the total sum of the junction capacitances between the sources and the drains of the memory cells M. The sum of the total sum Cox of the gate capacitances and the total sum Cj of the junction capacitances is the channel capacitance of the NAND cell NC. All the other capacitances including the overlapping capacitances of the selection gate lines SSL, GSL and the capacitances between the bit lines BLi and the sources/drains are very small relative to the total channel capacitance and hence are disregarded here.
Now, some of the scaling problems of such known NAND type EEPROMs will be discussed below. The capacitance between the word lines that are made of polysilicon and the P-type well regions is relatively large in known NAND type EEPROMs. Therefore, the potential of the word lines of the unselected blocks where no data is erased is raised by the capacitive coupling of the word lines and the P-type well regions. With this arrangement, the erase prohibition voltage that is used when erasing a data is obtained for conventional NAND type EEPROMs.
However, the balance of capacitances changes as memory cells are dimensionally scaled up or down. In other words, the capacitance between the word lines made of polysilicon and the P-type well regions can become smaller than ever relative to the overall capacitance depending on the memory cell structure. Then, the potential of the word lines of the unselected blocks may not be raised sufficiently to give rise to a problem of erasing data by accident.
Additionally, since the capacitance of the P-type well region is very large in a cell region, it takes a long time to raise the potential of the word lines of the unselected blocks by means of a booster circuit. In other words, data may be erased during the transition time until the predetermined erase voltage is reached. Then, it is difficult to determine the actual erasure time.
Conventionally, the write prohibition voltage is produced by capacitive coupling of the word lines and the NAND cell channel regions in a data write operation. Then, again, it may be difficult to sufficiently raise the voltage of the channel regions depending on the scaling of the NAND type EEPROM. Write errors may occur when the voltage rise is not sufficient. Such write errors may be prevented from taking place by selectively supplying a write prohibition voltage by way of bit lines. Then, however, the column related transistors including sense amplifiers need to be so designed as to withstand high voltages to consequently increase the chip area and make the entire manufacturing process to be a complex one.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array arranged on a semiconductor substrate,
the memory cell array being formed by arranging a plurality of memory cell units in array,
each of the plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines;
a word line selection circuit which selects one of the plurality of word lines;
a boosting circuit which boosts the potential of the semiconductor substrate and that of the plurality of word lines; and
a control circuit which controls the boosting circuit,
the control circuit being configured to increase the potential of the semiconductor substrate and that of all of the plurality of word lines to an erase voltage by means of the boosting circuit and to subsequently decrease the potential of the word line selected by the word line selection circuit, when data of a memory cell is erased.
According to a second aspect of the invention, there is provided a method of operating a semiconductor memory device comprising:
a memory cell array arranged on a semiconductor substrate, the memory cell array being formed by arranging a plurality of memory cell units in array, each of the plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines,
a word line selection circuit which selects one of the plurality of word lines,
a boosting circuit which boosts the potential of the semiconductor substrate and that of the plurality of word lines, and
a control circuit which controls the boosting circuit;
the method comprising
increasing the potential of the semiconductor substrate and that of all of the plurality of word lines to an erase voltage by means of the boosting circuit, and subsequently decreasing the potential of the word line selected by the word line selection circuit, when data of a memory cell is erased under the control of the control circuit.